`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    20:15:14 11/11/2011 
// Design Name: 
// Module Name:    pa 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module analyzer_module(
  input           CLK,
  input           RST,

  input   [31:0]  S_AWADDR,
  input           S_AWVALID,
  output          S_AWREADY,
  input   [31:0]  S_WDATA,
  input   [3:0]   S_WSTRB,
  input           S_WVALID,
  output          S_WREADY,
  output  [1:0]   S_BRESP,
  output          S_BVALID,
  input           S_BREADY,
  input   [31:0]  S_ARADDR,
  input           S_ARVALID,
  output          S_ARREADY,
  output  [31:0]  S_RDATA,
  output  [1:0]   S_RRESP,
  output          S_RVALID,
  input           S_RREADY,

  input           S_UP_TVALID,
  input   [127:0] S_UP_TDATA,
  input   [15:0]   S_UP_TSTRB,
  input           S_UP_TLAST,
  input           S_DN_TVALID,
  input  [127:0]  S_DN_TDATA,
  input  [15:0]    S_DN_TSTRB,
  input           S_DN_TLAST,

  output  [31:0]  M_UP_AWADDR,
  output  [7:0]   M_UP_AWLEN,
  output  [2:0]   M_UP_AWSIZE,
  output  [1:0]   M_UP_AWBURST,
  output          M_UP_AWVALID,
  input           M_UP_AWREADY,
  output  [127:0] M_UP_WDATA,
  output  [15:0]  M_UP_WSTRB,
  output          M_UP_WLAST,
  output          M_UP_WVALID,
  input           M_UP_WREADY,
  input   [1:0]   M_UP_BRESP,
  input           M_UP_BVALID,
  output          M_UP_BREADY,

  output  [31:0]  M_DN_AWADDR,
  output  [7:0]   M_DN_AWLEN,
  output  [2:0]   M_DN_AWSIZE,
  output  [1:0]   M_DN_AWBURST,
  output          M_DN_AWVALID,
  input           M_DN_AWREADY,
  output  [127:0] M_DN_WDATA,
  output  [15:0]  M_DN_WSTRB,
  output          M_DN_WLAST,
  output          M_DN_WVALID,
  input           M_DN_WREADY,
  input   [1:0]   M_DN_BRESP,
  input           M_DN_BVALID,
  output          M_DN_BREADY
  );
/*
  trigger_module
  trigger_module(
    .clk               (clk),
    .rst               (rst),

    .S_AWADDR         (S_AWADDR),
    .S_AWVALID        (S_AWVALID),
    .S_AWREADY        (S_AWREADY),
    .S_WDATA          (S_WDATA),
    .S_WSTRB          (S_WSTRB),
    .S_WVALID         (S_WVALID),
    .S_WREADY         (S_WREADY),
    .S_BRESP          (S_BRESP),
    .S_BVALID         (S_BVALID),
    .S_BREADY         (S_BREADY),
    .S_ARADDR         (S_ARADDR),
    .S_ARVALID        (S_ARVALID),
    .S_ARREADY        (S_ARREADY),
    .S_RDATA          (S_RDATA),
    .S_RRESP          (S_RRESP),
    .S_RVALID         (S_RVALID),
    .S_RREADY         (S_RREADY)
    );
*/
  capture_module
  capture(
    .clk              (CLK        ),
    .rst              (RST        ),

    .S_AWADDR         (S_AWADDR),
    .S_AWVALID        (S_AWVALID),
    .S_AWREADY        (S_AWREADY),
    .S_WDATA          (S_WDATA),
    .S_WSTRB          (S_WSTRB),
    .S_WVALID         (S_WVALID),
    .S_WREADY         (S_WREADY),
    .S_BRESP          (S_BRESP),
    .S_BVALID         (S_BVALID),
    .S_BREADY         (S_BREADY),
    .S_ARADDR         (S_ARADDR),
    .S_ARVALID        (S_ARVALID),
    .S_ARREADY        (S_ARREADY),
    .S_RDATA          (S_RDATA),
    .S_RRESP          (S_RRESP),
    .S_RVALID         (S_RVALID),
    .S_RREADY         (S_RREADY),

    .up_sel           (up_sel),
    .dn_sel           (dn_sel),
    .s_up_tvalid      (S_UP_TVALID ),
    .s_up_tdata       (S_UP_TDATA  ),
    .s_up_tstrb       (S_UP_TSTRB  ),
    .s_up_tlast       (S_UP_TLAST  ),
    .s_dn_tvalid      (S_DN_TVALID ),
    .s_dn_tdata       (S_DN_TDATA  ),
    .s_dn_tstrb       (S_DN_TSTRB  ),
    .s_dn_tlast       (S_DN_TLAST  ),
  
    .M_UP_AWADDR      (M_UP_AWADDR    ),
    .M_UP_AWLEN       (M_UP_AWLEN     ),
    .M_UP_AWSIZE      (M_UP_AWSIZE    ),
    .M_UP_AWBURST     (M_UP_AWBURST   ),
    .M_UP_AWVALID     (M_UP_AWVALID   ),
    .M_UP_AWREADY     (M_UP_AWREADY   ),
    .M_UP_WDATA       (M_UP_WDATA     ),
    .M_UP_WSTRB       (M_UP_WSTRB     ),
    .M_UP_WLAST       (M_UP_WLAST     ),
    .M_UP_WVALID      (M_UP_WVALID    ),
    .M_UP_WREADY      (M_UP_WREADY    ),
    .M_UP_BRESP       (M_UP_BRESP     ),
    .M_UP_BVALID      (M_UP_BVALID    ),
    .M_UP_BREADY      (M_UP_BREADY    ),
  
    .M_DN_AWADDR      (M_DN_AWADDR    ),
    .M_DN_AWLEN       (M_DN_AWLEN     ),
    .M_DN_AWSIZE      (M_DN_AWSIZE    ),
    .M_DN_AWBURST     (M_DN_AWBURST   ),
    .M_DN_AWVALID     (M_DN_AWVALID   ),
    .M_DN_AWREADY     (M_DN_AWREADY   ),
    .M_DN_WDATA       (M_DN_WDATA     ),
    .M_DN_WSTRB       (M_DN_WSTRB     ),
    .M_DN_WLAST       (M_DN_WLAST     ),
    .M_DN_WVALID      (M_DN_WVALID    ),
    .M_DN_WREADY      (M_DN_WREADY    ),
    .M_DN_BRESP       (M_DN_BRESP     ),
    .M_DN_BVALID      (M_DN_BVALID    ),
    .M_DN_BREADY      (M_DN_BREADY    )
    );
endmodule
